February 21, 2012
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removed bottleneck from data bus implementation, now meets timing even with keep_hierarchy
Stefan Schuermans authored on 2012-02-21 20:40:30
February 20, 2012
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begin of ethernet RX implementation, so far only test interface to core, does not meet timing
Stefan Schuermans authored on 2012-02-20 21:16:03
February 16, 2012
February 12, 2012
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implemented loading of data memory from firmware
Stefan Schuermans authored on 2012-02-12 17:47:50
February 11, 2012
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clock and reset constraints are for whole system
Stefan Schuermans authored on 2012-02-10 23:22:30
February 10, 2012
February 9, 2012
February 7, 2012
February 6, 2012
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implented basic system with core, instr memory, data memory
Stefan Schuermans authored on 2012-02-06 21:28:00
February 5, 2012
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second version of multiplier (slower, i.e. more stages -> faster clock)
Stefan Schuermans authored on 2012-02-05 21:39:45
January 25, 2012
January 24, 2012
January 23, 2012
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start of MIPS core: begin of decoder and ALU
Stefan Schuermans authored on 2012-01-23 22:06:18