mips_sys

added FIFO to UART TX
Parent 24e5d84
Stefan Schuermans

Stefan Schuermans commited on 2012-02-20 13:00:00
Showing 4 changed files, with 266 additions and 47 deletions.

blocks/fifo.vhd
View file @ 51e7135
... ... 
@@ -0,0 +1,128 @@
1 
+LIBRARY IEEE;
2 
+USE IEEE.STD_LOGIC_1164.ALL;
3 
+USE IEEE.NUMERIC_STD.ALL;
4 
+
5 
+ENTITY e_block_fifo IS
6 
+    GENERIC (
7 
+        addr_width: natural;
8 
+        data_width: natural
9 
+    );
10 
+    PORT (
11 
+        rst:       IN  std_logic;
12 
+        clk:       IN  std_logic;
13 
+        o_wr_rdy:  OUT std_logic;
14 
+        i_wr_data: IN  std_logic_vector(data_width - 1 DOWNTO 0);
15 
+        i_wr_en:   IN  std_logic;
16 
+        o_rd_rdy:  OUT std_logic;
17 
+        o_rd_data: OUT std_logic_vector(data_width - 1 DOWNTO 0);
18 
+        i_rd_en:   IN  std_logic
19 
+    );
20 
+END ENTITY e_block_fifo;
21 
+
22 
+ARCHITECTURE a_block_fifo OF e_block_fifo IS
23 
+
24 
+    COMPONENT e_block_rwram
25 
+        GENERIC (
26 
+            addr_width: natural;
27 
+            data_width: natural := 8
28 
+        );
29 
+        PORT (
30 
+            clk:       IN  std_logic;
31 
+            i_rd_addr: IN  std_logic_vector(addr_width - 1 DOWNTO 0);
32 
+            o_rd_data: OUT std_logic_vector(data_width - 1 DOWNTO 0);
33 
+            i_wr_addr: IN  std_logic_vector(addr_width - 1 DOWNTO 0);
34 
+            i_wr_data: IN  std_logic_vector(data_width - 1 DOWNTO 0);
35 
+            i_wr_en:   IN  std_logic
36 
+        );
37 
+    END COMPONENT e_block_rwram;
38 
+
39 
+    SUBTYPE t_addr_n IS natural RANGE 0 TO 2 ** addr_width - 1;
40 
+    SUBTYPE t_addr   IS std_logic_vector(addr_width - 1 DOWNTO 0);
41 
+    SUBTYPE t_data   IS std_logic_vector(data_width - 1 DOWNTO 0);
42 
+
43 
+    SIGNAL r_begin:       t_addr_n  := 0;
44 
+    SIGNAL r_end:         t_addr_n  := 0;
45 
+    SIGNAL r_end_dly1:    t_addr_n  := 0;
46 
+    SIGNAL r_end_dly2:    t_addr_n  := 0;
47 
+    SIGNAL r_begin_chgd:  std_logic := '0';
48 
+    SIGNAL r_ram_wr_addr: t_addr    := (OTHERS => '0');
49 
+    SIGNAL r_ram_wr_data: t_data    := (OTHERS => '0');
50 
+    SIGNAL r_ram_wr_en:   std_logic := '0';
51 
+
52 
+    SIGNAL s_ram_rd_addr: t_addr;
53 
+    SIGNAL s_rd_rdy:      std_logic;
54 
+    SIGNAL s_wr_rdy:      std_logic;
55 
+
56 
+    FUNCTION next_pos (
57 
+        pos: natural RANGE 0 TO 2 ** addr_width - 1
58 
+    ) RETURN natural IS
59 
+        VARIABLE v_next: natural RANGE 0 TO 2 ** addr_width - 1;
60 
+    BEGIN
61 
+        IF pos = 2 ** addr_width - 1 THEN
62 
+            v_next := 0;
63 
+        ELSE
64 
+            v_next := pos + 1;
65 
+        END IF;
66 
+        RETURN v_next;
67 
+    END FUNCTION next_pos;
68 
+
69 
+BEGIN
70 
+
71 
+    s_ram_rd_addr <= std_logic_vector(to_unsigned(r_begin, addr_width));
72 
+
73 
+    s_rd_rdy <= '0' WHEN r_begin = r_end OR r_begin_chgd = '1' ELSE '1';
74 
+    s_wr_rdy <= '0' WHEN r_begin = next_pos(r_end)             ELSE '1';
75 
+
76 
+    o_rd_rdy <= s_rd_rdy;
77 
+    o_wr_rdy <= s_wr_rdy;
78 
+
79 
+    i_rwram: e_block_rwram
80 
+        GENERIC MAP (
81 
+            addr_width => addr_width,
82 
+            data_width => data_width
83 
+        )
84 
+        PORT MAP (
85 
+            clk       => clk,
86 
+            i_rd_addr => s_ram_rd_addr,
87 
+            o_rd_data => o_rd_data,
88 
+            i_wr_addr => r_ram_wr_addr,
89 
+            i_wr_data => r_ram_wr_data,
90 
+            i_wr_en   => r_ram_wr_en
91 
+        );
92 
+
93 
+    p_fifo: PROCESS(rst, clk)
94 
+    BEGIN
95 
+        IF rst = '1' THEN
96 
+            r_begin       <= 0;
97 
+            r_end         <= 0;
98 
+            r_end_dly1    <= 0;
99 
+            r_end_dly2    <= 0;
100 
+            r_begin_chgd  <= '0';
101 
+            r_ram_wr_addr <= (OTHERS => '0');
102 
+            r_ram_wr_data <= (OTHERS => '0');
103 
+            r_ram_wr_en   <= '0';
104 
+        ELSIF rising_edge(clk) THEN
105 
+            -- read
106 
+            IF i_rd_en = '1' AND s_rd_rdy = '1' THEN
107 
+                r_begin      <= next_pos(r_begin);
108 
+                r_begin_chgd <= '1';
109 
+            ELSE
110 
+                r_begin_chgd <= '0';
111 
+            END IF;
112 
+            -- write
113 
+            IF i_wr_en = '1' AND s_wr_rdy = '1' THEN
114 
+                r_ram_wr_addr <= std_logic_vector(to_unsigned(r_end, addr_width));
115 
+                r_ram_wr_data <= i_wr_data;
116 
+                r_ram_wr_en   <= '1';
117 
+                r_end_dly2    <= next_pos(r_end);
118 
+            ELSE
119 
+                r_ram_wr_en  <= '0';
120 
+            END IF;
121 
+            -- delay r_end 2 cycles: 1 for writing to RAM, 1 to read RAM
122 
+            r_end_dly1 <= r_end_dly2;
123 
+            r_end      <= r_end_dly1;
124 
+        END IF;
125 
+    END PROCESS p_fifo;
126 
+
127 
+END ARCHITECTURE a_block_fifo;
128 
+
blocks/rwram.vhd
View file @ 51e7135
... ... 
@@ -0,0 +1,41 @@
1 
+LIBRARY IEEE;
2 
+USE IEEE.STD_LOGIC_1164.ALL;
3 
+USE IEEE.NUMERIC_STD.ALL;
4 
+
5 
+ENTITY e_block_rwram IS
6 
+    GENERIC (
7 
+        addr_width: natural;
8 
+        data_width: natural
9 
+    );
10 
+    PORT (
11 
+        clk:       IN  std_logic;
12 
+        i_rd_addr: IN  std_logic_vector(addr_width - 1 DOWNTO 0);
13 
+        o_rd_data: OUT std_logic_vector(data_width - 1 DOWNTO 0);
14 
+        i_wr_addr: IN  std_logic_vector(addr_width - 1 DOWNTO 0);
15 
+        i_wr_data: IN  std_logic_vector(data_width - 1 DOWNTO 0);
16 
+        i_wr_en:   IN  std_logic
17 
+    );
18 
+END ENTITY e_block_rwram;
19 
+
20 
+ARCHITECTURE a_block_rwram OF e_block_rwram IS
21 
+
22 
+    SUBTYPE t_addr IS std_logic_vector(addr_width - 1 DOWNTO 0);
23 
+    SUBTYPE t_data IS std_logic_vector(data_width - 1 DOWNTO 0);
24 
+    TYPE    t_buf  IS ARRAY(0 TO 2 ** addr_width - 1) OF t_data;
25 
+
26 
+    SIGNAL s_buf: t_buf;
27 
+
28 
+BEGIN
29 
+
30 
+    p_ram: PROCESS(clk)
31 
+    BEGIN
32 
+        IF rising_edge(clk) THEN
33 
+            IF i_wr_en = '1' THEN
34 
+                s_buf(to_integer(unsigned(i_wr_addr))) <= i_wr_data;
35 
+            END IF;
36 
+            o_rd_data <= s_buf(to_integer(unsigned(i_rd_addr)));
37 
+        END IF;
38 
+    END PROCESS p_ram;
39 
+
40 
+END ARCHITECTURE a_block_rwram;
41 
+
io/uart.vhd
View file @ 51e7135
... ... 
@@ -45,6 +45,12 @@ ARCHITECTURE a_io_uart OF e_io_uart IS
45 45 
     SIGNAL n_rx_data:    std_logic_vector(15 DOWNTO 0);
46 46 
     SIGNAL r_rx_data:    std_logic_vector(15 DOWNTO 0)    := X"0000";
47 47
48 
+    SIGNAL s_tx_wr_rdy:  std_logic;
49 
+    SIGNAL s_tx_wr_en:   std_logic;
50 
+    SIGNAL s_tx_rd_rdy:  std_logic;
51 
+    SIGNAL s_tx_rd_data: std_logic_vector(15 DOWNTO 0);
52 
+    SIGNAL s_tx_rd_en:   std_logic;
53 
+
48 54 
     SIGNAL n_tx_scale:  natural RANGE 2**16 - 1 DOWNTO 0;
49 55 
     SIGNAL r_tx_scale:  natural RANGE 2**16 - 1 DOWNTO 0 := 1;
50 56 
     SIGNAL n_tx_bits:   natural RANGE 15        DOWNTO 0;
... ... 
@@ -62,6 +68,23 @@ ARCHITECTURE a_io_uart OF e_io_uart IS
62 68 
     SIGNAL n_tx_data:   std_logic_vector(15 DOWNTO 0);
63 69 
     SIGNAL r_tx_data:   std_logic_vector(15 DOWNTO 0)    := X"0000";
64 70
71 
+    COMPONENT e_block_fifo IS
72 
+        GENERIC (
73 
+            addr_width: natural;
74 
+            data_width: natural
75 
+        );
76 
+        PORT (
77 
+            rst:       IN  std_logic;
78 
+            clk:       IN  std_logic;
79 
+            o_wr_rdy:  OUT std_logic;
80 
+            i_wr_data: IN  std_logic_vector(data_width - 1 DOWNTO 0);
81 
+            i_wr_en:   IN  std_logic;
82 
+            o_rd_rdy:  OUT std_logic;
83 
+            o_rd_data: OUT std_logic_vector(data_width - 1 DOWNTO 0);
84 
+            i_rd_en:   IN  std_logic
85 
+        );
86 
+    END COMPONENT e_block_fifo;
87 
+
65 88 
 BEGIN
66 89
67 90 
     p_cfg_next: PROCESS(r_cfg_scale, r_cfg_bits, r_cfg_stop,
... ... 
@@ -236,16 +259,36 @@ BEGIN
236 259 
         END IF;
237 260 
     END PROCESS p_rx_sync;
238 261
262 
+    s_tx_wr_en <= '1' WHEN i_addr = "10" AND i_wr_en(1 DOWNTO 0) = "11"
263 
+                  ELSE '0';
264 
+
265 
+    tx_fifo: e_block_fifo
266 
+        GENERIC MAP (
267 
+            addr_width => 4,
268 
+            data_width => 16
269 
+        )
270 
+        PORT MAP (
271 
+            rst       => rst,
272 
+            clk       => clk,
273 
+            o_wr_rdy  => s_tx_wr_rdy,
274 
+            i_wr_data => i_wr_data(15 DOWNTO 0),
275 
+            i_wr_en   => s_tx_wr_en,
276 
+            o_rd_rdy  => s_tx_rd_rdy,
277 
+            o_rd_data => s_tx_rd_data,
278 
+            i_rd_en   => s_tx_rd_en
279 
+        );
280 
+
239 281 
     p_tx_next: PROCESS(r_cfg_scale, r_cfg_bits, r_cfg_stop,
240 282 
                        r_tx_scale, r_tx_bits, r_tx_stop,
241 283 
                        r_tx_state, r_tx_cnt, r_tx_sample, r_tx_bit, r_tx_data,
242 
-                       i_addr, i_wr_data, i_wr_en)
284 
+                       s_tx_rd_rdy, s_tx_rd_data)
243 285 
         VARIABLE v_next_cnt:    boolean;
244 286 
         VARIABLE v_next_sample: boolean;
245 287 
         VARIABLE v_next_bit:    boolean;
246 288 
         VARIABLE v_next_state:  boolean;
247 289 
         VARIABLE v_bits:        natural RANGE 15 DOWNTO 0;
248 290 
     BEGIN
291 
+        s_tx_rd_en  <= '0';
249 292 
         n_tx_scale  <= r_tx_scale;
250 293 
         n_tx_bits   <= r_tx_bits;
251 294 
         n_tx_stop   <= r_tx_stop;
... ... 
@@ -260,7 +303,8 @@ BEGIN
260 303 
         v_next_state  := false;
261 304 
         v_bits        := 0;
262 305 
         IF r_tx_state = inactive THEN
263 
-            IF i_addr = "10" AND i_wr_en(1 DOWNTO 0) = "11" THEN
306 
+            IF s_tx_rd_rdy = '1' THEN
307 
+                s_tx_rd_en  <= '1';
264 308 
                 n_tx_scale  <= to_integer(unsigned(r_cfg_scale));
265 309 
                 n_tx_bits   <= to_integer(unsigned(r_cfg_bits));
266 310 
                 n_tx_stop   <= to_integer(unsigned(r_cfg_stop));
... ... 
@@ -268,7 +312,7 @@ BEGIN
268 312 
                 n_tx_cnt    <= 0;
269 313 
                 n_tx_sample <= 0;
270 314 
                 n_tx_bit    <= 0;
271 
-                n_tx_data   <= i_wr_data(15 DOWNTO 0);
315 
+                n_tx_data   <= s_tx_rd_data;
272 316 
             END IF;
273 317 
         ELSE
274 318 
             v_next_cnt := true;
... ... 
@@ -359,9 +403,7 @@ BEGIN
359 403 
                     o_rd_data(19 DOWNTO 16) <= r_cfg_bits;
360 404 
                     o_rd_data(25 DOWNTO 24) <= r_cfg_stop;
361 405 
                 WHEN "01" =>
362 
-                    IF r_tx_state = inactive THEN
363 
-                        o_rd_data(0) <= '1';
364 
-                    END IF;
406 
+                    o_rd_data(0) <= s_tx_wr_rdy;
365 407 
                 WHEN OTHERS =>
366 408 
                     NULL;
367 409 
             END CASE;
mips_sys.xise
View file @ 51e7135
... ... 
@@ -16,58 +16,58 @@
16 16
17 17 
   <files>
18 18 
     <file xil_pn:name="mips/decoder.vhd" xil_pn:type="FILE_VHDL">
19 
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="6"/>
20 
-      <association xil_pn:name="Implementation" xil_pn:seqID="6"/>
19 
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="7"/>
20 
+      <association xil_pn:name="Implementation" xil_pn:seqID="7"/>
21 21 
     </file>
22 22 
     <file xil_pn:name="mips/types.vhd" xil_pn:type="FILE_VHDL">
23 23 
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
24 24 
       <association xil_pn:name="Implementation" xil_pn:seqID="1"/>
25 25 
     </file>
26 26 
     <file xil_pn:name="mips/alu.vhd" xil_pn:type="FILE_VHDL">
27 
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="8"/>
28 
-      <association xil_pn:name="Implementation" xil_pn:seqID="8"/>
27 
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="9"/>
28 
+      <association xil_pn:name="Implementation" xil_pn:seqID="9"/>
29 29 
     </file>
30 30 
     <file xil_pn:name="mips/core.vhd" xil_pn:type="FILE_VHDL">
31 
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="11"/>
32 
-      <association xil_pn:name="Implementation" xil_pn:seqID="11"/>
31 
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="13"/>
32 
+      <association xil_pn:name="Implementation" xil_pn:seqID="13"/>
33 33 
     </file>
34 34 
     <file xil_pn:name="mips/regs.vhd" xil_pn:type="FILE_VHDL">
35 
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
36 
-      <association xil_pn:name="Implementation" xil_pn:seqID="3"/>
35 
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="4"/>
36 
+      <association xil_pn:name="Implementation" xil_pn:seqID="4"/>
37 37 
     </file>
38 38 
     <file xil_pn:name="mips/shifter.vhd" xil_pn:type="FILE_VHDL">
39 39 
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
40 40 
       <association xil_pn:name="Implementation" xil_pn:seqID="2"/>
41 41 
     </file>
42 42 
     <file xil_pn:name="mips/cmp.vhd" xil_pn:type="FILE_VHDL">
43 
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="7"/>
44 
-      <association xil_pn:name="Implementation" xil_pn:seqID="7"/>
43 
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="8"/>
44 
+      <association xil_pn:name="Implementation" xil_pn:seqID="8"/>
45 45 
     </file>
46 46 
     <file xil_pn:name="mips/div.vhd" xil_pn:type="FILE_VHDL">
47 
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="5"/>
48 
-      <association xil_pn:name="Implementation" xil_pn:seqID="5"/>
47 
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="6"/>
48 
+      <association xil_pn:name="Implementation" xil_pn:seqID="6"/>
49 49 
     </file>
50 50 
     <file xil_pn:name="mips/mul_slow.vhd" xil_pn:type="FILE_VHDL">
51 
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="4"/>
52 
-      <association xil_pn:name="Implementation" xil_pn:seqID="4"/>
51 
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="5"/>
52 
+      <association xil_pn:name="Implementation" xil_pn:seqID="5"/>
53 53 
     </file>
54 54 
     <file xil_pn:name="system/system.vhd" xil_pn:type="FILE_VHDL">
55 
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="22"/>
56 
-      <association xil_pn:name="Implementation" xil_pn:seqID="22"/>
55 
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="24"/>
56 
+      <association xil_pn:name="Implementation" xil_pn:seqID="24"/>
57 57 
     </file>
58 58 
     <file xil_pn:name="test/testbed.vhd" xil_pn:type="FILE_VHDL">
59 
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="23"/>
59 
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="25"/>
60 60 
       <association xil_pn:name="PostMapSimulation" xil_pn:seqID="128"/>
61 61 
       <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="128"/>
62 62 
       <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="128"/>
63 63 
     </file>
64 64 
     <file xil_pn:name="fw/rom.vhd" xil_pn:type="FILE_VHDL">
65 
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="17"/>
66 
-      <association xil_pn:name="Implementation" xil_pn:seqID="17"/>
65 
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="19"/>
66 
+      <association xil_pn:name="Implementation" xil_pn:seqID="19"/>
67 67 
     </file>
68 68 
     <file xil_pn:name="io/leds.vhd" xil_pn:type="FILE_VHDL">
69 
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="14"/>
70 
-      <association xil_pn:name="Implementation" xil_pn:seqID="14"/>
69 
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="16"/>
70 
+      <association xil_pn:name="Implementation" xil_pn:seqID="16"/>
71 71 
     </file>
72 72 
     <file xil_pn:name="constraints/leds.ucf" xil_pn:type="FILE_UCF">
73 73 
       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
... ... 
@@ -76,54 +76,62 @@
76 76 
       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
77 77 
     </file>
78 78 
     <file xil_pn:name="io/cyc_cnt.vhd" xil_pn:type="FILE_VHDL">
79 
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="16"/>
80 
-      <association xil_pn:name="Implementation" xil_pn:seqID="16"/>
79 
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="18"/>
80 
+      <association xil_pn:name="Implementation" xil_pn:seqID="18"/>
81 81 
     </file>
82 82 
     <file xil_pn:name="io/lcd.vhd" xil_pn:type="FILE_VHDL">
83 
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="15"/>
84 
-      <association xil_pn:name="Implementation" xil_pn:seqID="15"/>
83 
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="17"/>
84 
+      <association xil_pn:name="Implementation" xil_pn:seqID="17"/>
85 85 
     </file>
86 86 
     <file xil_pn:name="io/lcd_pins.vhd" xil_pn:type="FILE_VHDL">
87 
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="10"/>
88 
-      <association xil_pn:name="Implementation" xil_pn:seqID="10"/>
87 
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="11"/>
88 
+      <association xil_pn:name="Implementation" xil_pn:seqID="11"/>
89 89 
     </file>
90 90 
     <file xil_pn:name="constraints/lcd.ucf" xil_pn:type="FILE_UCF">
91 91 
       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
92 92 
     </file>
93 93 
     <file xil_pn:name="fw/ram.0.vhd" xil_pn:type="FILE_VHDL">
94 
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="21"/>
95 
-      <association xil_pn:name="Implementation" xil_pn:seqID="21"/>
94 
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="23"/>
95 
+      <association xil_pn:name="Implementation" xil_pn:seqID="23"/>
96 96 
     </file>
97 97 
     <file xil_pn:name="fw/ram.1.vhd" xil_pn:type="FILE_VHDL">
98 
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="20"/>
99 
-      <association xil_pn:name="Implementation" xil_pn:seqID="20"/>
98 
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="22"/>
99 
+      <association xil_pn:name="Implementation" xil_pn:seqID="22"/>
100 100 
     </file>
101 101 
     <file xil_pn:name="fw/ram.2.vhd" xil_pn:type="FILE_VHDL">
102 
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="19"/>
103 
-      <association xil_pn:name="Implementation" xil_pn:seqID="19"/>
102 
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="21"/>
103 
+      <association xil_pn:name="Implementation" xil_pn:seqID="21"/>
104 104 
     </file>
105 105 
     <file xil_pn:name="fw/ram.3.vhd" xil_pn:type="FILE_VHDL">
106 
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="18"/>
107 
-      <association xil_pn:name="Implementation" xil_pn:seqID="18"/>
106 
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="20"/>
107 
+      <association xil_pn:name="Implementation" xil_pn:seqID="20"/>
108 108 
     </file>
109 109 
     <file xil_pn:name="io/switches_pins.vhd" xil_pn:type="FILE_VHDL">
110 
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="9"/>
111 
-      <association xil_pn:name="Implementation" xil_pn:seqID="9"/>
110 
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="10"/>
111 
+      <association xil_pn:name="Implementation" xil_pn:seqID="10"/>
112 112 
     </file>
113 113 
     <file xil_pn:name="io/switches.vhd" xil_pn:type="FILE_VHDL">
114 
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="13"/>
115 
-      <association xil_pn:name="Implementation" xil_pn:seqID="13"/>
114 
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="15"/>
115 
+      <association xil_pn:name="Implementation" xil_pn:seqID="15"/>
116 116 
     </file>
117 117 
     <file xil_pn:name="constraints/switches.ucf" xil_pn:type="FILE_UCF">
118 118 
       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
119 119 
     </file>
120 120 
     <file xil_pn:name="io/uart.vhd" xil_pn:type="FILE_VHDL">
121 
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="12"/>
122 
-      <association xil_pn:name="Implementation" xil_pn:seqID="12"/>
121 
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="14"/>
122 
+      <association xil_pn:name="Implementation" xil_pn:seqID="14"/>
123 123 
     </file>
124 124 
     <file xil_pn:name="constraints/uart.ucf" xil_pn:type="FILE_UCF">
125 125 
       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
126 126 
     </file>
127 
+    <file xil_pn:name="blocks/fifo.vhd" xil_pn:type="FILE_VHDL">
128 
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="12"/>
129 
+      <association xil_pn:name="Implementation" xil_pn:seqID="12"/>
130 
+    </file>
131 
+    <file xil_pn:name="blocks/rwram.vhd" xil_pn:type="FILE_VHDL">
132 
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
133 
+      <association xil_pn:name="Implementation" xil_pn:seqID="3"/>
134 
+    </file>
127 135 
   </files>
128 136
129 137 
   <properties>
130 138