mips_sys

extended testbed to log ethernet TX data
Parent 6e87eaa
Stefan Schuermans

Stefan Schuermans commited on 2012-03-21 21:42:47
Showing 1 changed files, with 34 additions and 20 deletions.

test/testbed.vhd
View file @ 00e6828
... ... 
@@ -48,37 +48,37 @@ ARCHITECTURE a_testbed OF e_testbed IS
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         );
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     SIGNAL s_clk:           std_logic;
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+    SIGNAL s_leds:          std_logic_vector(7 DOWNTO 0);
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+    SIGNAL s_lcd:           t_io_lcd_pins;
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+    SIGNAL s_uart_loopback: std_logic;
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     SIGNAL s_eth_clk:       std_logic;
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-    SIGNAL s_eth_rxd:         std_logic_vector(3 DOWNTO 0);
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+    SIGNAL s_eth_rxd_d:     std_logic_vector(3 DOWNTO 0);
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+    SIGNAL s_eth_rxd:       std_logic_vector(4 DOWNTO 0);
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     SIGNAL s_eth_rx_dv:     std_logic;
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-    SIGNAL pin_leds:          std_logic_vector(7 DOWNTO 0);
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-    SIGNAL pin_lcd:           t_io_lcd_pins;
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-    SIGNAL pin_uart_loopback: std_logic;
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-    SIGNAL pin_eth_rxd:       std_logic_vector(4 DOWNTO 0);
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-    SIGNAL pin_eth_txd:       std_logic_vector(3 DOWNTO 0);
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-    SIGNAL pin_eth_tx_en:     std_logic;
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+    SIGNAL s_eth_txd:       std_logic_vector(3 DOWNTO 0);
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+    SIGNAL s_eth_tx_en:     std_logic;
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 BEGIN
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     system: e_system
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         PORT MAP (
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             clk              => s_clk,
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-            pin_o_leds       => pin_leds,
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-            pin_o_lcd        => pin_lcd,
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+            pin_o_leds       => s_leds,
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+            pin_o_lcd        => s_lcd,
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             pin_i_switches   => (sw => (OTHERS => '0'), OTHERS => '0'),
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-            pin_i_uart_rx    => pin_uart_loopback,
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-            pin_o_uart_tx    => pin_uart_loopback,
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+            pin_i_uart_rx    => s_uart_loopback,
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+            pin_o_uart_tx    => s_uart_loopback,
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             pin_i_eth_rx_clk => s_eth_clk,
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-            pin_i_eth_rxd    => pin_eth_rxd,
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+            pin_i_eth_rxd    => s_eth_rxd,
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             pin_i_eth_rx_dv  => s_eth_rx_dv,
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             pin_i_eth_crs    => s_eth_rx_dv,
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             pin_i_eth_col    => '0',
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             pin_i_eth_tx_clk => s_eth_clk,
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-            pin_o_eth_txd    => pin_eth_txd,
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-            pin_o_eth_tx_en  => pin_eth_tx_en
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+            pin_o_eth_txd    => s_eth_txd,
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+            pin_o_eth_tx_en  => s_eth_tx_en
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         );
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-    pin_eth_rxd <= "0" & s_eth_rxd;
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+    s_eth_rxd <= "0" & s_eth_rxd_d;
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     p_clk: PROCESS
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     BEGIN
... ... 
@@ -100,22 +100,36 @@ BEGIN
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         END LOOP;
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     END PROCESS p_eth_clk;
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-    p_eth_data: PROCESS
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+    p_eth_rx_data: PROCESS
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     BEGIN
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-        s_eth_rxd   <= "0000";
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+        s_eth_rxd_d <= "0000";
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         s_eth_rx_dv <= '0';
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         WAIT FOR 25 ms;
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         WAIT UNTIL s_eth_clk = '1';
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         WAIT UNTIL s_eth_clk = '0';
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         FOR i IN 0 TO eth_data'length - 1 LOOP
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-            s_eth_rxd   <= eth_data(i);
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+            s_eth_rxd_d <= eth_data(i);
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             s_eth_rx_dv <= '1';
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             WAIT UNTIL s_eth_clk = '1';
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             WAIT UNTIL s_eth_clk = '0';
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         END LOOP;
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-        s_eth_rxd   <= "0000";
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+        s_eth_rxd_d <= "0000";
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         s_eth_rx_dv <= '0';
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         WAIT;
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-    END PROCESS p_eth_data;
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+    END PROCESS p_eth_rx_data;
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+
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+    p_eth_tx_data: PROCESS
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+        VARIABLE l: line;
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+    BEGIN
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+        FOR i IN 0 TO eth_data'length - 1 LOOP
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+            WAIT UNTIL s_eth_clk = '0';
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+            WAIT UNTIL s_eth_clk = '1';
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+            IF s_eth_tx_en = '1' THEN
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+                write(l, "ethernet TX: ");
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+                write(l, to_integer(unsigned(s_eth_txd)));
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+                writeline(output, l);
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+            END IF;
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+        END LOOP;
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+    END PROCESS p_eth_tx_data;
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 END ARCHITECTURE a_testbed;
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