mips_sys

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-- MIPS I system
-- Copyright 2011-2012 Stefan Schuermans <stefan@blinkenarea.org>
-- Copyleft GNU public license V2 or later
--          http://www.gnu.org/copyleft/gpl.html
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE work.io_eth_pins.all;
USE work.io_lcd_pins.all;
USE work.io_switches_pins.all;
ENTITY e_system IS
    PORT (
        clk:            IN  std_logic;
        pin_o_leds:     OUT std_logic_vector(7 DOWNTO 0);
        pin_o_lcd:      OUT t_io_lcd_pins;
        pin_i_switches: IN  t_io_switches_pins;
        pin_i_uart_rx:  IN  std_logic;
        pin_o_uart_tx:  OUT std_logic;
        pin_o_eth:      OUT t_io_eth_o_pins;
        pin_i_eth:      IN  t_io_eth_i_pins
    );
END ENTITY e_system;
ARCHITECTURE a_system OF e_system IS
    CONSTANT c_instr_addr_width: natural := 14;
    CONSTANT c_data_addr_width:  natural := 13;
    SIGNAL rst: std_logic := '0';
    SIGNAL s_instr_addr:   std_logic_vector(31 DOWNTO 0);
    SIGNAL s_instr_data:   std_logic_vector(31 DOWNTO 0);
    SIGNAL s_core_req:     std_logic;
    SIGNAL s_core_grant:   std_logic;
    SIGNAL s_core_addr:    std_logic_vector(31 DOWNTO 0);
    SIGNAL s_core_rd_data: std_logic_vector(31 DOWNTO 0);
    SIGNAL s_core_rd_en:   std_logic_vector( 3 DOWNTO 0);
    SIGNAL s_core_wr_data: std_logic_vector(31 DOWNTO 0);
    SIGNAL s_core_wr_en:   std_logic_vector( 3 DOWNTO 0);
    SIGNAL s_ethbm_req:     std_logic;
    SIGNAL s_ethbm_grant:   std_logic;
    SIGNAL s_ethbm_addr:    std_logic_vector(31 DOWNTO 0);
    SIGNAL s_ethbm_rd_data: std_logic_vector(31 DOWNTO 0);
    SIGNAL s_ethbm_rd_en:   std_logic_vector( 3 DOWNTO 0);
    SIGNAL s_ethbm_wr_data: std_logic_vector(31 DOWNTO 0);
    SIGNAL s_ethbm_wr_en:   std_logic_vector( 3 DOWNTO 0);
    SIGNAL s_dbus_addr:    std_logic_vector(31 DOWNTO 0);
 
 
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